Some uses of electrically programmable memories pose strong constraints in terms of available space, such as in the case of an implementation on a microprocessor card, also called chip card. In these uses, it is routine practice to use FLASH memories, which offer the advantage of a very simple structure and compactness, making it possible to achieve a high storage capacity on a reduced surface area. However, these FLASH memories require significant currents to be applied for their programming, which induces high leakage currents and an overall high energy consumption. Now, for implementations on a contactless chip card for example, the available energy is very low since such a chip card does not generally have an built-in power source and is simply remotely powered by an external reader.
By way of illustration, FIG. 1 illustrates a sector of a conventional FLASH type electrically programmable non-volatile memory, organized in a memory plane according to a matrix of n×n cells Cij arranged in lines and columns, each being located at the intersection of a word line WLi and of a bit line BLj. Each cell Cij comprises a floating gate transistor with its gate G connected to the word line WLi, its drain D connected to the bit line BLj and its source S connected to a source line SL. In such a prior art structure, the term “physical memory page” is used to designate a set of the memory cells connected to one and the same word line WLi. The sector of a memory is a set of pages in which the source lines LS are interconnected and are at the same electrical potential.
In such a memory, each cell Cij, represented in FIG. 2 by a floating gate transistor, can contain a binary information item, which can be modified by a programming operation to set this value to “1”, which includes trapping electrical charges in the floating gate of the transistor, or by an erasure operation to set this value to “0”, by extracting charges from the floating gate. As an example, the programming of such a cell of a FLASH memory according to the method known as CHISEL, an acronym standing for Channel Initiated Secondary Electron, proposes to set the potential VD of its drain D linked to a bit line to the value of 3.8 V, the potential of its source VS to 0 V, and the potential VB of its well to a negative value, for example −0.5 V, for an operating temperature of 25° C. These conditions induce a programming current in each cell of 24 nA, or a current of 12 μA circulating in a bit line for a sector comprising 512 cells on a bit line (n=512).
It should be noted that this CHISEL programming method relies on increasing the voltage between the drain and the well of each cell, which is advantageous for the effectiveness of the programming but which also induces an increased leakage current for each bit line, which amounts to 25 μA in the numerical example chosen. The result of this is a total consumed current of 37 μA on a bit line, which is significant, and, for example, exceeds the acceptable maximum for an implementation within a contactless chip card.
Thus, there is a need for an electrically programmable non-volatile memory which makes it possible to satisfy the dual constraint of a high density and a low energy consumption.